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Features
* * * * *
Vcc = 5V 5% Military Temperature Range Fully Compatible with the TS68040 Five Low Skew Outputs - Five Outputs (Q0-Q4) with Output-to-Output Skew < 500 ps Each Being Phase End Frequency Locked to the SYNC Input Three Additional Outputs are Available: - The 2X_Q Output Runs Twice the System "Q" Frequency - The Q/2 Output Runs At 1/2 the System "Q" Frequency - The Q5 Output is Inverted (180 Phase Shift) Two Selectable Clock Inputs - Two Selectable CLOCK Inputs are Available for Test or Redundancy Purposes - Test Mode Pin (PLL_EN) Provided for Low Frequency Testing - All Outputs Can Go Into High Impedance (3-state) for Board Test Purposes Input Frequency Range From 5 MHz to 2X_Q FMAX Three Input/Output Ratios - Input/Output Phase-locked Frequency Ratios of 1:2, 1:1 and 2:1 are Available Low Part-to-part Skew - The Phase Variation from Part-to-part Between the SYNC and FEEDBACK Inputs is Less than 550 ps (Derived From the tPD Specification, which Defines the Part-to-part Skew) CMOS and TTL Compatible - All Outputs Can Drive Either CMOS or TTL Inputs - All Inputs are TTL-level Compatible LOCK Indicator (LOCK) Indicates a Phase-locked State
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* * *
* *
Low Skew CMOS PLL Clock Driver Tri-State 70 and 100 MHz Versions TS88915T
Description
The TS88915T Clock Driver utilizes a phazed-locked loop (PLL) technology to lock its low skew outputs' frequency and phase onto an input reference clock. It is designed to provide clock distribution for high performance microprocessors such as TS68040, TSPC603E,TSPC603P,TSPC603R, PCI bridge, RAM's, MMU's.
Screening/Quality
This Product is Manufactured: * * Based Upon the Generic Flow of MIL-STD-883 or According to Atmel-Grenoble Standard
R suffix PGA 29 Ceramic Pin Grid Array
W suffix LDCC 28 Leaded Ceramic Chip Carrier
Rev. 2122A-HIREL-06/02
1
Introduction
The TS88915T is a CMOS PLL Clock Driver using phase-locked loop (PLL) technology. The PLL allows the high current and low skew outputs to lock onto a single input and distribute it with essentially zero delay to multiple components on a board. The PLL also allows the TS88915T to multiply a low frequency input clock and distribute it locally at a higher (2X) system frequency. Multiple 88915's can lock onto a single reference clock, which is ideal for applications when a central system clock must be distributed synchronously to multiple boards (see Figure 12).
Figure 1. TS88915T Block Diagram (All Versions)
FEEDBACK LOCK
SYNC[0]
0 M U 1X
PHASE/FREQ. DETECTOR
CHARGE PUMP/ LOOP FILTER
SYNC[1]
VOLTAGE CONTROLLED OSCILLATOR
REF_SEL
EXT. REC NETWORK (RC1 pin)
PLL_EN
0 MUX
1
2X_Q
D (/1) 1 M U 0X D CP FREQ_SEL OE/RST D CP R R CP R
Q Q
Q0
DIVIDE BY TWO
(/2)
Q Q
Q1
Q Q
Q2
D CP R
Q Q
Q3
D CP R
Q Q
Q4
D CP R
Q Q
Q5
D CP R
Q Q
Q/2
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Pin Assignments
29-lead Pin Grid Array (PGA)
Figure 2. 29-lead PGA (Bottom View)
F F/SL E GNDA D VCCA C SYC0 B FDBK A NC VCC GND Q4 Q*2 RST Q5 VCC Q/2 GND R/SL Q3 VCC RC1 TS88915T (BOTTOM VIEW) GND Q2 SYC1 GND Q1 P/EN LOCK Q0 VCC GND
1
2
3
4
5
6
28-lead Ceramic Leaded Chip Carrier (LDCC)
Figure 3. 28-lead LDCC (Top View)
OE/RST VCC Q5 GND Q4 4 3 2 1 28 VCC 2X_Q 27 26 25 24 23 TS88915T (TOP VIEW) 22 21 20 19 12 13 14 15 16 17 18
FEEDBACK REF_SEL SYNC[0] VCC (AN) RC1 GND (AN) SYNC[1]
5 6 7 8 9 10 11
Q/2 GND Q3 VCC Q2 GND LOCK
FREQ_SEL GND Q0 VCC
Q1 GND PLL_EN
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Signal Description
Table 1. Signal Index
Pin Name SYNC[0] SYNC[1] REF_SEL FREQ_SEL FEEDBACK RC1 Q(0-4) Q5 2x_Q Q/2 LOCK OE/RST PLL_EN VCC, GND Num 1 1 1 1 1 1 5 1 1 1 1 1 1 11 I/O Input Input Input Input Input Input Output Output Output Output Output Input Input Power Signal Function Reference Clock Input Reference Clock Input Chooses Reference Between SYNC[0] and SYNC[1] Doubles VCO Internal Frequency Feedback Input to Phase Detector Input for External RC Network Clock Output (Locked to SYNC) Inverse of Clock Output 2 x Clock Output (Q) Frequency (Synchronous) Clock Output (Q) Frequency / 2 (Synchronous) Indicates Phase Lock has been Achieved (High when Locked) Output Enable/Asynchronous Reset (Active Low) Disables Phase-lock for Low Frequency Testing Power and Ground pins Pins 8 and 10 are "analog" supply pins for internal PLL only
Scope Applicable Documents Requirements
General Design and Construction
Terminal Connections
This drawing describes the specific requirements for the clock driver TS88915T, in compliance with MIL-STD-883 class B or Atmel standard screening. 1. MIL-STD-883: Test methods and procedures for electronics. 2. MIL-PRF-38535 appendix A: General specifications for microcircuits.
The microcircuits are in accordance with the applicable documents and as specified herein.
Depending on the package, the terminal connections shall be as shown in Figure 2 and Figure 3. Lead material and finish shall be as specified in MIL-STD-1835 (see "Package Mechanical Data" on page 17). The macrocircuits are packaged in hermetically sealed ceramic packages, which conform to case outlines of MIL-STD-1835, but "Package Mechanical Data" on page 17. The precise case outlines are described at the end of the specification (see "Package Mechanical Data" on page 178) and into MIL-STD-1835.
Lead Material and Finish
Package
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Absolute Maximum Ratings
Stresses above the absolute maximum rating may cause permanent damage to the device. Extended operation at the maximum levels may degrade performance and affect reliability. Table 2. Absolute Maximum Rating for the TS88915T
Parameter Supply Voltage Input Voltage Storage Temperature Range Power Dissipation PGA Package LDCC Package Thermal Resistance Junction-Case PGA29 LDCC28 Note: Symbol VCC Vin Tstg PD Min -0.5 -0.5 -65 Max 6.0 VCC + 0.5 +150 500 Unit V V C mW
JC
-
7 7
C/W
Functional operating conditions are given in AC and DC electrical specifications. Stresses beyond the absolute maximums listed may affect device reliability or cause permanent damage to the device. Caution: Input voltage must not be greater than the supply voltage by more than 2.5V at all times including during power-on reset.
Mechanical and Environment Marking
The microcircuits shall meet all environmental requirements of either MIL-STD-883 for class B devices or for Atmel standard screening. The document that defines the markings is identified in the related reference documents. Each microcircuit is legible and permanently marked with the following information as minimum: * * * * * * Atmel Logo Manufacturer's Part Number Class B Identification Date-code of Inspection Lot ESD Identifier If Available Country of Manufacturing
Electrical Characteristics
General Requirements
All static and dynamic electrical characteristics specified for inspection purposes and the relevant measurement conditions are given below: * * Table Static Electrical Characteristics for the Electrical Variants Table Dynamic Electrical Characteristics for TS88915T (70 MHz and 100 MHz Versions)
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Static Characteristics
DC Electrical Characteristics (Voltages Referenced to GND) Tc = -55C to +125C for 70 MHz and 100 MHz version; VCC = 5.0V 5%
Symbol VIH VIL VOH Parameter Minimum High-Level Input Voltage Maximum Low-Level Input Voltage Minimum High-Level Output Voltage Test Conditions Vout = 0.1V or VCC - 0.1V Vout = 0.1V or VCC - 0.1V Vin = VIH or VIL, IOH = -36 mA(1) Vin = VIH or VIL, IOL = 36 mA(1) VOL Iin ICCT ICC IOZ Notes: 1. 2. 3. 4. 5. 6. Maximum Low-Level Output Voltage Vin = VIH or VIL, IOL = 15 mA(6) Maximum Input Leakage Current Maximum ICC/Input Maximum Quiescent Supply Current (per package) VI = VCC or GND, VCCmax VI = VCC - 2.1V, VCCmax VI = VCC or GND, VCCmax VCCmin VCCmax Limits 2.0 0.8 4.01 4.51 0.44(4) 0.50(5) 0.20 1.0 2.0
(2)
Unit V V V
V A mA mA A
1.0 $50
Maximum Tri-State Leakage Current VI = VIH or VIL,VO = VCC or GND, VCCmax IOL and IOH are 12 mA and -12 mA respectively for the LOCK output. The PLL_EN input pin is not guaranteed to meet this specification. Maximum test duration is 2.0 ms, one output loaded at a time. Specification value for static tests at 25C and at minimum rated operating temperature. Specification value for static tests at maximum rated operating temperature. Specifications values which can be used for compability with the Power PC.
Capacitance and Power Specifications
Symbol CIN CPD PD1 PD2 Note: Parameter Input Capacitance Power Dissipation Capacitance Power Dissipation at 50 MHz with 50 Thevenin Termination Power Dissipation at 50 MHz with 50 Parallel Termination to GND 1. PD1 and PD2 mW/Output are for a `Q' output. Typical Values 10 40 23 mW/Output 184 mW/Device 57 mW/Output 456 mW/Device Unit pF pF mW mW Conditions VCC = 5.0V VCC = 5.0V VCC = 5.0V T = 25C VCC = 5.0V T = 25C
Dynamic Characteristics
Frequency Specifications
(Tc = -55C to +125C, VCC = 5.0V 5%)
Guaranteed Minimum Symbol fmax(1) Note: Parameter Maximum Operating Frequency (2X_Q Output) 88915T-70 70 88915T-100 100 Unit MHz
Maximum Operating Frequency (Q0-Q4, Q5 Outputs) 35 50 MHz 1. Maximum Operating Frequency is guaranteed with the part in a phase-locked condition, and all outputs loaded with 50 terminated to VCC/2.
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SYNC Input Timing Requirements
Minimum Symbol tRISE/FALL, SYNC Inputs tCYCLE, SYNC Inputs Parameter Rise/Fall Time, SYNC Inputs From 0.8 to 2.0V Input Clock Period, SYNC Inputs 88915T-70 - 28.5(1) 88915T-100 - 20.0(1) Maximum 3.0 200(2) Unit ns ns
Duty Cycle SYNC Inputs Input Duty Cycle, SYNC Inputs 50% 25% Notes: 1. These tCYCLE minimum values are valid when `Q' output is feed back and connected to the FEEDBACK pin. 2. Information in Table 1 and in Note 3 of the AC specification notes describe this specification and its limits depending on what output is feed back, and if FREQ_SEL is high or low.
AC Characteristics (Tc = -55C to +125C, VCC = 5.0V 5%, Load = 50 terminated to VCC/2)
Symbol tRISE/FALL Outputs tRISE/FALL(1) 2X_Q Output tPULSE WIDTH(1) (Q0-Q4, Q5, Q/2) tPULSE WIDTH(1) (2X_Q Output) Parameter Rise/Fall Time, All Outputs (Between 0.2 VCC and 0.8 VCC) Rise/Fall Time into a 20 pF Load, with Termination(2) Output Pulse Width: Q0, Q1, Q2, Q3, Q4, Q5, Q/2 at VCC/2 Output Pulse Width: 2X_Q at 1.5V 40 MHz 50 MHz 66 MHz 100 MHz 40-49 MHz 50-65 MHz 66-100 MHz Min 1.0 Max 2.5 Unit ns Conditions Into a 50 Load Terminated to VCC/2 tRISE: 0.8V - 2.0V tFALL: 2.0V - 0.8V Into a 50 Load Terminated to VCC/2 Must use termination(2)
0.5 0.5tCYCLE - 0.5(2)
1.6 0.5tCYCLE + 0.5(2)
ns ns
0.5tCYCLE - 1.5(2) 0.5tCYCLE - 1.0 0.5tCYCLE - 0.5 0.5tCYCLE - 0.5 0.5tCYCLE - 1.5(2) 0.5tCYCLE - 1.0 0.5tCYCLE - 0.5
0.5tCYCLE + 1.5(2) 0.5tCYCLE + 1.0 0.5tCYCLE + 0.5 0.5tCYCLE + 0.5 0.5tCYCLE + 1.5(2) 0.5tCYCLE + 1.0 0.5tCYCLE + 0.5
ns
tPULSE WIDTH(1) (2X_Q Output)
Output Pulse Width: 2X_Q at VCC/2
ns
Into a 50 Load Terminated to VCC/2 See Note 4 and Figure 6 for detailed explanation
tPD(1)(3) SYNC Feedback
SYNC Input to Feedback Delay (Measured at SYNC0 or 1 and FEEDBACK input pins)
(With 1 M from RC1 to An VCC) 70 MHz 100 MHz -1.05 -1.05 -0.40 -0.30
ns
(With 1 M from RC1 to An GND) +1.25 tSKEWr (Rising)(5)
(1)(4)
+3.25 500 ps All Outputs into a matched 50 load Terminated to VCC/2 All Outputs into a matched 50 load Terminated to VCC/2 All Outputs into a matched 50 load Terminated to VCC/2
Output-to-Output Skew between Outputs Q0-Q4, Q/2 (Rising edges only)
-
tSKEWf (1)(4) (Falling)
Output-to-Output Skew between Outputs Q0-Q4 (Falling edges only)
-
750
ps
tSKEWall (1)(4) (Falling)
Output-to-Output Skew 2X_Q, Q/2, Q0-Q4 Rising, Q5 Falling
-
750
ps
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AC Characteristics (Tc = -55C to +125C, VCC = 5.0V 5%, Load = 50 terminated to VCC/2) (Continued)
Symbol tLOCK(5) tPZL Parameter Time required to acquire Phase-Lock from time SYNC inputs signal is received Output Enable Time OE/RST to 2X_Q, Q0Q4, Q5 and Q/2 Output Disable Time OE/RST to 2X_Q, Q0Q4, Q5 and Q/2 Min 1.0 3.0 Max 10 14 Unit ms ns Conditions Also time to lock indicator High Measured with the PLL_EN pin Low
tPHZ, tPLZ
Notes:
1. 2. 3. 4. 5.
Measured with the PLL_EN pin Low These specifications are not tested, they are guaranteed by statistical characterization. See General AC specification Note 1. tCYCLE in this specification is 1/Frequency at which the particular output is running. The TPD specification's min/max values may shift closer to zero of a larger pull up resistor is used. Under equally loaded conditions and at a fixed temperature and voltage. With VCC fully powered-on, and an output properly connected to the FEEDBACK pin. tLOCK maximum is with C1 = 0.1 F, tLOCK minimum is with C1 = 0.01 F.
3.0
14
ns
Figure 4. Output/Input Switching Waveforms and Timing Diagrams (These waveforms represent the hook-up configuration of Figure 8)
SYNC INPUT (SYNC[1] or SYNC[0])
tCYCLE SYNC INPUT tPD
FEEDBACK INPUT
Q/2 OUTPUT
tSKEWall
tSKEWr
tSKEWf
tSKEWr
Q0-Q4 OUTPUTS tCYCLE "Q" OUTPUTS
Q5 OUTPUT
2X_Q OUTPUT
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Application Information
General AC Specification 1. Several specifications can only be measured when the TS88915T is in phaselocked operation. TS88915T units are fabricated with key transistor properties Notes
intentionally varied to create a 14 cell designed experimental matrix. 2. These two specs (tRISE/FALL and tPULSE WIDTH 2X_Q output) guarantee that the TS88915T meets the 33 MHz TS68040 P-Clock input specification (at 66 MHz). For these two specs to be guaranteed by Atmel, the termination scheme shown below in Figure 5 must be used. Figure 5. TS68040 P-Clock Input Termination Scheme
TS88915 2X_Q Output Rs Z0 (CLOCK TRACE) TS68040 P_Clock Input Rp Rp = 1.5Z0
Rs = Z0-7
3. To meet the 25 MHz TS68040 P-clock input specification (2 x Q tpulse width at 50 MHz) FREQ-SEL must be low. This configuration improve the accuracy of the 88915T duty cycle. 4. The wiring diagrams and explanations in Figure 8, Figure 9 and Figure 10 demonstrate the input and output frequency relationships for three possible feedback configurations. The allowable SYNC input range for each case is also indicated. There are two allowable SYNC frequency ranges, depending whether FREQ_SEL is high or low. Although not shown, it is possible to feed back the Q5 output, thus creating a 180 phase shift between the SYNC input and the "Q" outputs. Table 3 below summarizes the allowable SYNC frequency range for each possible configuration. Table 3. Allowable SYNC Input Frequency Range for Different Feedback Configurations
FREQ_SEL Level HIGH HIGH HIGH HIGH LOW LOW LOW LOW FEEDBACK Output Q/2 any "Q" (Q0-Q4) Q5 2X_Q Q/2 any "Q" (Q0-Q4) Q5 2X_Q Allowable SYNC Input Frequency Range (MHz) 5 to (2X_Q FMAX Spec)/4 10 to (2X_Q FMAX Spec)/2 10 to (2X_Q FMAX Spec)/2 20 to (2X_Q FMAX Spec) 2.5 to (2X_Q FMAX Spec)/8 5 to (2X_Q FMAX Spec)/4 5 to (2X_Q FMAX Spec)/4 10 to (2X_Q FMAX Spec)/2 Corresponding VCO Frequency Range 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) 20 to (2X_Q FMAX Spec) Phase Relationships of the "Q" Outputs to Rising SYNC Edge 0 0 180 0 0 0 180 0
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5. A 1 M resistor tied to either Analog VCC or Analog GND as shown in Figure 5 is required to ensure no jitter is present on the TS88915T outputs. This technique causes a phase offset between the SYNC input and the output connected to the FEEDBACK input, measured at the input pins. The TPD spec describes how this offset varies with process, temperature and voltage. The specs are arrived at by measuring the phase relationship for the 14 lots described in Note 1 while the part was in phase-locked operation. The actual measurements are made with 10 MHz SYNC input (1.0 ns edge rate from 0.8V - 2.0V) with the Q/2 output feed back. The phase measurements are made at 1.5V. The Q/2 output is terminated at the FEEDBACK input with 100 to VCC and 100 to GND. Figure 6. Depiction of the Fixed SYNC to Feedback Offset (tPD) Which is Present When a 1 M Resistor is Tied to VCC or GND
EXTERNAL LOOP FILTER RC1 330 0.1 F R2 C1 1 M REFERENCE RESISTOR ANALOG GND With the 1 M resistor tied in this fashion, the tPD specification measured at the input pins is: tPD = -0.775 ns 0.275 ns 1 M REFERENCE RESISTOR RC1
R2
330
C1
0.1 F
With the 1 M resistor tied in this fashion, the tPD specification measured at the input pins is: tPD = 2.25 ns 1.0 ns
3.0V SYNC INPUT 2.25 ns OFFSET FEEDBACK OUTPUT 5.0V FEEDBACK OUTPUT SYNC INPUT
3.0V -0.775 ns OFFSET 5.0V
6. The tSKEWr specification guarantees that the rising edges of outputs Q/2, Q0, Q1, Q2, Q3 and Q4 will always fall within a 500 ps window within one part. However, if the relative position of each output within this window is not specified, the 500 ps window must be added to each side of the tPD specification limits to calculate the total part-to-part skew. For this reason the absolute distribution of these outputs is provided in Table 4. When taking the skew data, Q0 was used as a reference, so all measurements are relative to this output. The information in Table 4 is derived from measurements taken from the 14 process lots described in Note 1, over the temperature and voltage range.
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Table 4. Relative Position of Outputs Q/2, Q0-Q4, 2X_Q,Within the 500 ps tSKEWr Spec Window
Output Q0 Q1 Q2 Q3 Q4 Q/2 2X_Q (ps) 0 -72 -44 -40 -274 -16 -633 + (ps) 0 40 275 255 -34 250 -35
7. Calculation of Total Output-to-Output skew Between Multiple Parts (Part-to-Part Skew) By combining the tPD specification and the information in Note 5, the worst case Output-to-Output skew between multiple TS88915's connected in parallel can be calculated. This calculation assumes that all parts have a common SYNC input clock with equal delay that input signal to each part. This skew value is valid at the TS88915 output pins only (equally loaded), it does not include PCB trace delays due to varying loads.With a 1 M resistor tied to analog VCC as shown in Note 4, the tPD spec. limits between SYNC and the Q/2 output (connected to the FEEDBACK pin) are -1.05 ns and -0.5 ns. To calculate the skew of any given output between two or more parts, the absolute value of the distribution of that output given in Table 4 must be subtracted and added to the lower and upper tPD spec limits respectively. For output Q2, [276-(-44)] = 320 ps is the absolute value of the distribution. Therefore [-1.05 - 0.32] = -1.37 ns is the lower tPD limit, and [0.5 + 0.32] = -0.18 ns is the upper limit. Therefore the worst case skew of output Q2 between any number of part is [(-1.37)-(-0.18)] = 1.19 ns. Q2 has the worst case skew distribution of any output, so 1.2 ns is the absolute worst case Output-to-Output skew between multiple parts. 8. Note 4 explains that the tPD specification was measured and is guaranteed for the configuration of the Q/2 output connected to the FEEDBACK pin and the SYNC input running at 10 MHz. The fixed offset (tPD) as described above has some dependence on the input frequency and what frequency the VCO is running. The graphs of Figure 6 demonstrate this dependence. The data presented in Figure 6 is from devices representing process extremes, and the measurements were also taken at the voltage extremes (VCC = 5.25V and 4.75V). Therefore the data in Figure 6 is a realistic representation of the variation of tPD.
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Figure 7.
-0.50 -0.50
-0.75
tPD SYNC to FEEDBACK -1.00 (ns)
-1.25
tPD -1.00 SYNC to FEEDBACK (ns)
-1.50
-1.50 2.5
-2.00 5.0 7.5 10.0 12.5 15.0 17.5 2.5 5.0 7.5 10 12.5 15 17.5 20 22.5 25 27.5 SYNC INPUT FREQUENCY (MHz) SYNC INPUT FREQUENCY (MHz)
tPD versus Frequency for Q/2 output feed back, including process and voltage variation at 25C (with 1 M resistor tied to analog VCC)
tPD versus Frequency for Q4 output feed back, including process and voltage variation at 25C (with 1 M resistor tied to analog VCC)
3.5 3.0 2.5
3.5 3.0
tPD SYNC to FEEDBACK (ns)
2.5 2.0 1.5 1.0 0.5 2.5 5.0 7.5 10.0 12.5 15.0 17.5 SYNC INPUT FREQUENCY (MHz)
tPD SYNC to FEEDBACK (ns)
2.0 1.5 1.0 0.5 0 5 10 15 20 25 SYNC INPUT FREQUENCY (MHz)
tPD versus Frequency for Q/2 output feed back, including process and voltage variation at 25C (with 1 M resistor tied to analog GND)
tPD versus Frequency for Q4 output feed back, including process and voltage variation at 25C (with 1 M resistor tied to analog GND)
9. The Lock indicator pin (LOCK) will reliably indicate a phase-locked condition at SYNC input frequencies down to 10 MHz. At frequencies below 10 MHz, the frequency of correction pulses going into the phase detector from the SYNC and FEEDBACK pins may not be sufficient to allow the lock indicator circuitry to accurately predict a phase-locked condition. The TS88915T is guaranteed to provide stable phase-locked operation down to the appropriate minimum input frequency given in Table 3, even though the LOCK pin may be low at frequencies below 10 MHz.
Timing Notes
1. The TS88915T aligns rising edges of the FEEDBACK input and the SYNC input, therefore the SYNC input does not require a 50% duty cycle. 2. All skew specs are measured between VCC/2 crossing point of the appropriate output edges. All skews are specified as `windows', not as a "deviation around a center point". 3. If a "Q" output is connected to the FEEDBACK input (this situation is not shown), the "Q" output frequency would match the SYNC input frequency, the 2X_Q out-
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put would run twice the SYNC frequency, and the Q/2 output would run at half the SYNC frequency. See Figure 7, Figure 8 and Figure 9 below. Figure 8. Wiring Diagram and Frequency Relationship with Q/2 Output Feed Back
100 MHz SIGNAL 25 MHz FEEDBACK SIGNAL
HIGH
RST Q5 Q4 2X_Q Q/2
FEEDBACK LOW CRYSTAL 25 MHz INPUT
OSC. EXTERNAL LOOP FILTER
REF_SEL SYNC[0] ANALOG VCC RC1 ANALOG GND
Q3 Q2
50 MHz "Q" CLOCK OUTPUTS
FQ_SEL
Q0
Q1
PLL_EN
HIGH
HIGH
Figure 9. Wiring Diagram and Frequency Relationship with Q4 Output Feed Back
50 MHz FEEDBACK SIGNAL
HIGH
RST Q5 Q4 2X_Q Q/2
100 MHz SIGNAL
FEEDBACK LOW
CRYSTAL 50 MHz INPUT OSC. EXTERNAL LOOP FILTER
25 MHz SIGNAL
REF_SEL SYNC[0] ANALOG VCC RC1 ANALOG GND
Q3 Q2
50 MHz "Q" CLOCK OUTPUTS
FQ_SEL
Q0
Q1
PLL_EN
HIGH HIGH
Figure 10. Wiring Diagram and Frequency Relationship with 2X_Q Output Feed Back
100 MHz FEEDBACK SIGNAL
HIGH
RST Q5 Q4 2X_Q Q/2
FEEDBACK LOW REF_SEL
CRYSTAL 100 MHz INPUT SYNC[0] OSC. EXTERNAL LOOP FILTER
25 MHz SIGNAL
Q3
ANALOG VCC RC1 ANALOG GND
Q2
50 MHz "Q" CLOCK OUTPUTS
FQ_SEL
Q0
Q1
PLL_EN
HIGH
HIGH
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Notes Concerning Loop Filter and Board Layout Issues
1. Figure 10 shows a loop filter and analog isolation scheme which will be effective in most applications. The following guidelines should be followed to ensure stable and jitter-free operation: 2. All loop filter and analog isolation components should be tied as close to the package as possible. Stray current passing through the parasitics of long traces can cause undesirable voltage transients at the RC1 pin. 3. The 47 resistors, the 10 F low frequency bypass capacitor, and the 0.1 F high frequency bypass capacitor form a wide bandwidth filter that will minimize the 88915T's sensitivity to voltage transients from the system digital VCC supply and ground planes. This filter will typically ensure that a 100 mV step deviation on the digital VCC supply will cause no more than 100 ps phase deviation on the 88915T outputs. A 250 mV step deviation on VCC using the recommended filter values should cause no more than a 250 ps phase deviation; if a 25 F bypass capacitor is used (instead of 1 F) a 250 mV VCC step should cause no more than a 100 ps phase deviation. If good bypass techniques are used on a board design near components which may cause digital VCC and ground noise, the above described VCC step deviations should not occur at the 88915T's digital VCC supply. The purpose of the bypass filtering scheme shown in Figure 10 is to give the 88915T additional protection from the power supply and ground plane transients that can occur in a high frequency, high speed digital system. 4. There are no special requirements set forth for the loop filter resistors (1 M and 330). The loop filter capacitor (0.1 F) can be a ceramic chip capacitor, the same as a standard bypass capacitor. 5. The 1 M reference resistor injects current into the internal charge pump of the PLL, causing a fixed offset between the outputs and the SYNC input. This also prevents excessive jitter caused by inherent PLL dead-band. If the VCO (2X_Q output) is running above 40 MHz, the 1 M resistor provides the correct amount of current injection into the charge pump (2-3 A). For the 70 and 100 MHz versions, if the VCO is running below 40 MHz, a 1.5 M resistor should be used (instead of 1 M). 6. In addition to the bypass capacitors used in the analog filter of Figure 10, there should be a 0.1 F bypass capacitor between each of the other (digital) four VCC pins and the board ground plane. This will reduce output switching noise caused by the 88915T outputs, in addition to reducing potential for noise in the `analog' section of the chip. These bypass capacitors should also be tied as close to the package as possible.
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Figure 11. Recommended Loop Filter and Analog Isolation Scheme for the TS88915T
BOARD VCC
47 ANALOG VCC 10 F LOW FREQ BYPASS 0.1 F HIGH FREQ BYPASS 1 M 330 RC1 ANALOG LOOP FILTER/FCO SECTION OF THE TS88915T (NOT DRAWN TO SCALE)
ANALOG GND 47
Note:
A separate analog power supply is not necessary and should not be used. Following these prescribed guidelines is all that is necessary to use the TS88915T in a normal digital environment.
Figure 12. Representation of a Potential Multi-Processing Application Utilizing the TS88915T for Frequency Multiplication and Low Board-to-board Skew
CMMU TS88915T PLL 2f CMMU CPU CARD
CLOCK at f
CPU
CMMU
CMMU SYSTEM CLOCK SOURCE CMMU TS88915T PLL DISTRIBUTE CLOCK at f 2f CPU
CMMU
CMMU
CPU CARD
CMMU
CMMU CLOCK at 2f AT POINT OF USE
CMMU
TS88915T PLL 2f
MEMORY CONTROL
MEMORY CARDS CLOCK at 2f AT POINT OF USE
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TS88915T System Level Testing Functionality
Tri-State functionality has been added to the TS88915T to ease system board testing. Bringing the OE/RST pin low will put all outputs (except for LOCK) into a high impedance state. As long as the PLL_EN pin is low, the Q0-Q4, Q5 and Q/2 outputs will remain in the low state after the OE/RST until a falling SYNC edge is seen. The 2X_Q output will be the inverse of the SYNC signal in this mode. If the tri-state functionality will be used, a pull-up or a pull-down resistor must be tied to the FEEDBACK input pin to prevent it from floating when the feedback output goes into high impedance. With the PLL_EN pin low the selected SYNC signal is gated directly into the signal clock distribution network, bypassing and disabling the VCO. In this mode the outputs are directly driven by the SYNC input (per the block diagram). This mode can also be used for low frequency board testing. Note: If the outputs are put into 3-state during normal PLL operation, the loop will be broken and phase-lock will be lost. It will take a maximum of 10 ms (tLOCK spec) to regain phase-lock after the OE/RST pin goes back high.
Preparation For Delivery
Packaging
Microcircuits are prepared for delivery in accordance with MIL-PRF-38535.
Certificate of Compliance Atmel offers a certificate of compliances with each shipment of parts, affirming the products are in compliance either with MIL-STD-883 and guarantying the parameters not tested at temperature extremes for the entire temperature range.
Handling
MOS devices must be handled with certain precautions to avoid damage due to accumulation of static charge. Input protection devices have been designed in the chip to minimize the effect of this static buildup. However, the following handling practices are recommended: * * * * * * Devices Should Be Handled On Benches With Conductive And Grounded Surfaces Ground Test Equipment, Tools And Operator Do Not Handle Devices By The Leads. Store Devices In Conductive Foam Or Carriers. Avoid Use Of Plastic, Rubber, Or Silk In Mos Areas. Maintain Relative Humidity Above 50 Percent If Practical.
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TS88915T
Package Mechanical Data
29-pin PGA
Inches Dim A C D E F G H 0.017 Min 0.594 0.17 0.045 0.045 0.100 BSC 0.019 0.43 Max 0.606 0.107 0.19 0.055 0.055 Min 15.087 4.32 1.143 1.143
Millimeters Max 15.392 2.72 4.83 1.397 1.397 2.54 BSC 0.48
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28-pin LDCC
Note:
This package is pin compatible with PLCC
Ordering Information
TS88915T M R B/T 70
Device Type
Maximum Output Frequency : 70: 70 MHz 100: 100 MHz
Temperature range : Tc M : -55, +125C V : -40, +85C
Screening level : __ : Standard B/T: according to MIL-STD-883 D/T: Burn-in Package : R: PGA W: LDCC
Note:
For availability of the different versions, contact your Atmel sales office.
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Atmel Headquarters
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e-mail
literature@atmel.com
Web Site
http://www.atmel.com
(c) Atmel Corporation 2002. Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company's standard warranty which is detailed in Atmel's Terms and Conditions located on the Company's web site. The Company assumes no responsibility for any errors which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel's products are not authorized for use as critical components in life support devices or systems. ATMEL (R) is the registered trademark of Atmel. The PowerPC names and the PowerPC logotype are trademarks of International Business Machines Corporation, used under license therform. Other terms and product names may be the trademarks of others. Printed on recycled paper.
2122A-HIREL-06/02 0M

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